The present invention relates to a method of demodulating a PSK modulated signal and to a circuit arrangement for practicing the method.
PSK modulation is understood by the person skilled in the art to be a modulation method which operates with so-called phase shift keying. In systems utilizing this modulation method, circuits containing phase-locked control loops are utilized to demodulate the subcarriers or data, respectively. Two types of such circuits which are commonly used to demodulate the subcarrier are the squaring loop and the Costas loop. Both of these control loops include a phase detector, a control filter and an oscillator which can be varied in its frequency by a control voltage.
In each of these circuits, if a difference in phase exists between the input signal and the reference signal generated by the oscillator, the phase detector will generate a control signal which is smoothed by the control filter and varies the oscillator frequency in such a manner that the difference in phase becomes minimal. Since with PSK modulated input signals the polarity of these signals changes in the rhythm of the data modulation by .+-. 180.degree., the phase detector of the control loop must be designed so that these phase shifts in the input signal will not influence the control signal of the oscillator. Such prior art control loops are shown in FIGS. 1 and 2.
In the squaring loop of FIG. 1, the input signal (.+-.A.sub.1 sin.omega..sub.u t) is fed through a bandpass filter 1 to a squaring or doubler stage 2 and then through a bandpass filter 3, which is tuned to the double frequency, to a chopper 4. The output signal from the chopper 4, which is proportional to the phase shift between the input signal and the reference voltage from a reference oscillator 6, is smoothed in the loop filter 5 and controls the frequency of the oscillator 6. In order to generate the output signal, the frequency of the oscillator 6 is divided in half in a frequency divider, the phase of the resulting signal is shifted by 90.degree. in a phase shifter 8 and is then fed, together with the input signal of the loop, to a further chopper 9. The output signal of the chopper 9 can be mathematically described as EQU .+-. A.sub.2 sin.sup.2 .omega..sub.u t,
where the sign always includes the binary data information.
In the Costas loop, as shown in FIG. 2, the input signal (.+-. A.sub.1 sin .omega..sub.u t) is fed in parallel to two choppers 21 and 28. The output signals from the choppers 21 and 28 are smoothed by lowpass filters 22 and 29 respectively and fed to an analog multiplier 23. The output signal of the multiplier 23 is smoothed in the control filter 24, and used to control the frequency of the reference oscillator 25 so that the oscillator oscillates at twice the input frequency. The output signal from the oscillator 25 is fed to a frequency divider 26 wherein the frequency is cut in half and the resulting signal is fed to the chopper 21 as the reference voltage. The reference voltage for chopper 28 must be shifted in phase by 90.degree. with respect to the input signal, and this is accomplished in a phase shifting stage 27. The demodulated signal appears at the output of chopper 28.
As can be seen, the known control loops are very complex in structure.